{"id":56448,"date":"2023-10-17T00:15:44","date_gmt":"2023-10-16T16:15:44","guid":{"rendered":"\/\/www.viralrail.com\/blog\/56448.html"},"modified":"2023-10-17T00:15:44","modified_gmt":"2023-10-16T16:15:44","slug":"fkyjupdds","status":"publish","type":"post","link":"\/\/www.viralrail.com\/blog\/56448.html","title":{"rendered":"FPGA\u53ef\u4ee5\u5c06UART\u8dd1\u5230\u591a\u5c11\uff1f"},"content":{"rendered":"
FPGA\uff08Field Programmable Gate Array\uff09\u662f\u4e00\u79cd\u53ef\u7f16\u7a0b\u7684\u95e8\u9635\u5217\uff0c\u53ef\u4ee5\u7528\u6765\u5b9e\u73b0\u590d\u6742\u7684\u903b\u8f91\u529f\u80fd\u3002UART\uff08Universal Asynchronous Receiver\/Transmitter\uff09\u662f\u4e00\u79cd\u5f02\u6b65\u4e32\u884c\u6570\u636e\u4f20\u8f93\u6280\u672f\uff0c\u53ef\u4ee5\u7528\u6765\u4f20\u8f93\u6570\u636e\u3002\u672c\u6587\u5c06\u63a2\u8ba8FPGA\u53ef\u4ee5\u5c06UART\u8dd1\u5230\u591a\u5c11\uff0c\u4ee5\u53ca\u5982\u4f55\u4f7f\u7528FPGA\u6765\u5b9e\u73b0UART\u7684\u9ad8\u901f\u4f20\u8f93\u3002<\/p>\n
FPGA\u53ef\u4ee5\u5c06UART\u8dd1\u5230\u975e\u5e38\u9ad8\u7684\u901f\u5ea6\uff0c\u6700\u9ad8\u53ef\u4ee5\u8fbe\u5230\u6bcf\u79d2\u6570\u767e\u4e07\u6b21\u7684\u4f20\u8f93\u901f\u5ea6\u3002<\/strong>\u5b9e\u9645\u7684\u4f20\u8f93\u901f\u5ea6\u53d6\u51b3\u4e8eFPGA\u7684\u5904\u7406\u80fd\u529b\uff0c\u4ee5\u53caUART\u7684\u914d\u7f6e\u3002UART\u7684\u914d\u7f6e\u53ef\u4ee5\u5728\u4e0d\u540c\u7684\u65f6\u949f\u9891\u7387\u4e0b\u8fdb\u884c\u8c03\u6574\uff0c\u4ece\u800c\u8fbe\u5230\u66f4\u9ad8\u7684\u4f20\u8f93\u901f\u5ea6\u3002<\/p>\n FPGA\u5177\u6709\u591a\u79cd\u7279\u6027\uff0c\u53ef\u4ee5\u5e2e\u52a9\u5b9e\u73b0UART\u7684\u9ad8\u901f\u4f20\u8f93\u3002\u4f8b\u5982\uff0cFPGA\u53ef\u4ee5\u652f\u6301\u591a\u4e2aUART\u901a\u9053\uff0c\u53ef\u4ee5\u5b9e\u73b0\u5e76\u53d1\u4f20\u8f93\uff0c\u4ece\u800c\u63d0\u9ad8\u4f20\u8f93\u901f\u5ea6\u3002\u6b64\u5916\uff0cFPGA\u8fd8\u652f\u6301\u591a\u79cd\u6570\u636e\u5904\u7406\u529f\u80fd\uff0c\u53ef\u4ee5\u5b9e\u73b0\u6570\u636e\u538b\u7f29\u3001\u52a0\u5bc6\u7b49\uff0c\u4ece\u800c\u6539\u5584\u4f20\u8f93\u6548\u7387\u3002<\/p>\n UART\u7684\u914d\u7f6e\u53ef\u4ee5\u5728\u4e0d\u540c\u7684\u65f6\u949f\u9891\u7387\u4e0b\u8fdb\u884c\u8c03\u6574\uff0c\u4ece\u800c\u8fbe\u5230\u66f4\u9ad8\u7684\u4f20\u8f93\u901f\u5ea6\u3002\u6b64\u5916\uff0cUART\u7684\u914d\u7f6e\u8fd8\u53ef\u4ee5\u8c03\u6574\u6570\u636e\u5e27\u683c\u5f0f\uff0c\u4ee5\u6539\u5584\u4f20\u8f93\u6548\u7387\u3002<\/p>\n \u4f7f\u7528\u9ad8\u6027\u80fd\u7684FPGA\u53ef\u4ee5\u63d0\u9ad8UART\u7684\u4f20\u8f93\u901f\u5ea6\uff0c\u56e0\u4e3a\u9ad8\u6027\u80fd\u7684FPGA\u53ef\u4ee5\u652f\u6301\u66f4\u9ad8\u7684\u65f6\u949f\u9891\u7387\uff0c\u4ece\u800c\u6539\u5584UART\u7684\u4f20\u8f93\u6548\u7387\u3002\u6b64\u5916\uff0c\u9ad8\u6027\u80fd\u7684FPGA\u8fd8\u53ef\u4ee5\u652f\u6301\u66f4\u591a\u7684UART\u901a\u9053\uff0c\u4ece\u800c\u5b9e\u73b0\u5e76\u53d1\u4f20\u8f93\uff0c\u63d0\u9ad8\u4f20\u8f93\u901f\u5ea6\u3002<\/p>\n FPGA\u53ef\u4ee5\u5c06UART\u8dd1\u5230\u975e\u5e38\u9ad8\u7684\u901f\u5ea6\uff0c\u6700\u9ad8\u53ef\u4ee5\u8fbe\u5230\u6bcf\u79d2\u6570\u767e\u4e07\u6b21\u7684\u4f20\u8f93\u901f\u5ea6\u3002<\/strong>\u8981\u5b9e\u73b0UART\u7684\u9ad8\u901f\u4f20\u8f93\uff0c\u9700\u8981\u4f7f\u7528FPGA\u7684\u7279\u6027\uff0c\u8c03\u6574UART\u7684\u914d\u7f6e\uff0c\u4ee5\u53ca\u4f7f\u7528\u9ad8\u6027\u80fd\u7684FPGA\u3002\u672c\u6587\u4ecb\u7ecd\u4e86\u5982\u4f55\u4f7f\u7528FPGA\u6765\u5b9e\u73b0UART\u7684\u9ad8\u901f\u4f20\u8f93\uff0c\u4ee5\u53caFPGA\u53ef\u4ee5\u5c06UART\u8dd1\u5230\u591a\u5c11\uff0c\u5e0c\u671b\u5bf9\u5927\u5bb6\u6709\u6240\u5e2e\u52a9\u3002<\/p>\n","protected":false},"excerpt":{"rendered":" FPGA\uff08FieldProgrammableGateArray\uff09\u662f\u4e00\u79cd\u53ef\u7f16\u7a0b\u7684\u95e8\u9635\u5217\uff0c\u53ef\u4ee5\u7528\u6765\u5b9e\u73b0\u590d\u6742\u7684\u903b\u8f91\u529f\u80fd\u3002UART\uff08UniversalAsynchrono<\/p>\n","protected":false},"author":1,"featured_media":4132,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"site-sidebar-layout":"default","site-content-layout":"default","ast-global-header-display":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","footnotes":""},"categories":[36],"tags":[145],"class_list":["post-56448","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-blog","tag-uart"],"_links":{"self":[{"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/posts\/56448"}],"collection":[{"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/comments?post=56448"}],"version-history":[{"count":0,"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/posts\/56448\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/media\/4132"}],"wp:attachment":[{"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/media?parent=56448"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/categories?post=56448"},{"taxonomy":"post_tag","embeddable":true,"href":"\/\/www.viralrail.com\/wp-json\/wp\/v2\/tags?post=56448"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}\u5982\u4f55\u4f7f\u7528FPGA\u6765\u5b9e\u73b0UART\u7684\u9ad8\u901f\u4f20\u8f93\uff1f<\/h2>\n
1. \u4f7f\u7528FPGA\u7684\u7279\u6027<\/h3>\n
2. \u8c03\u6574UART\u7684\u914d\u7f6e<\/h3>\n
3. \u4f7f\u7528\u9ad8\u6027\u80fd\u7684FPGA<\/h3>\n
\u603b\u7ed3<\/h2>\n